ASIC Verification Engineer
|Published||May 24, 2023|
|Location||San Jose, CA|
What You'll Do
It used to be that high-speed packet forwarding was performed in dedicated ASIC designs. These days we are looking to make those ASICs more general and programmable. Cisco Common ASIC Group is looking for an expert Senior Verification Engineer to drive existing projects and engage in new development of our next generation switching systems.
As part of ASIC team, you will be developing the ASICs at the heart of each of these switch products. There are only a very few teams worldwide that implement such devices. Every time you access the Internet, chances are, your data's been through one of our switches.
Who You'll Work With
You will work with Cisco’s best-in-class switching solution team. Our team is responsible for driving integration of the Nexus systems and ACI with software, including OpenStack, Docker, and Open vSwitch, to help our customers build multitenant clouds.
Who You Are
You are a talented, motivated ASIC verification engineer to join the team and contribute to the verification of very complex ASICs. You will have a Design Verification background, hands-on experience in System Verilog and UVM methodology, with in-depth knowledge of ASIC design and verification flow.
You’ll be part of Cisco Common ASIC Group, focusing on developing various test benches and contributing to different aspects of verification infrastructure.
You will collaborate closely with the design team and the hardware team to verify the ASIC in simulation, in emulation and during ASIC bring up.
Designing UVM/C++ test benches
Defining new DV methodologies
Maintaining existing test benches
End-to-end verification of various design blocks
Contributing to top level verification
Be a part of emulation testing efforts
Participate in the ASIC bringup
Education and Experience Required:
Bachelor’s or Master’s degree in EE and CE with coursework in digital design, VLSI and project work using Verilog/System Verilog
Prior ASIC Design Verification experience is preferred but not mandatory
Knowledge and Skills:
Hands-on and deep understanding of System Verilog and UVM methodology
Ability to construct testbench including scoreboard, agents, sequencers, and monitors.
Ability to debug issues independently
Scripting experience (Python, Perl, TCL, shell programming)
Good written and verbal communication skills
Collaborative and team-focused, with the drive to learn and grow
#WeAreCisco. We are all unique, but collectively we bring our talents to work as a team, to develop innovative technology and power a more inclusive, digital future for everyone. How do we do it? Well, for starters - with people like you!
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We tackle whatever challenges come our way. We have each other’s backs, we recognize our accomplishments, and we grow together. We celebrate and support one another - from big and small things in life to big career moments. And giving back is in our DNA (we get 10 days off each year to do just that).
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Cisco is an Affirmative Action and Equal Opportunity Employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis.
Cisco will consider for employment, on a case by case basis, qualified applicants with arrest and conviction records.